-cd memories read_two_mux.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l read_two_mux.v.log
-cd memories no_implicit_en.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l no_implicit_en.v.log
-cd memories simple_sram_byte_en.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l simple_sram_byte_en.v.log
-cd memories amber23_sram_byte_en.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l amber23_sram_byte_en.v.log
-cd memories firrtl_938.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l firrtl_938.v.log
-cd memories implicit_en.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l implicit_en.v.log
-cd memories shared_ports.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l shared_ports.v.log
-cd memories issue00710.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l issue00710.v.log
-cd memories issue00335.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l issue00335.v.log
-cd asicworld code_tidbits_syn_reset.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_tidbits_syn_reset.v.log
-cd asicworld code_hdl_models_mux_using_assign.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_mux_using_assign.v.log
-cd asicworld code_verilog_tutorial_decoder_always.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_decoder_always.v.log
-cd asicworld code_hdl_models_dff_async_reset.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_dff_async_reset.v.log
-cd asicworld code_tidbits_blocking.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_tidbits_blocking.v.log
-cd asicworld code_verilog_tutorial_v2k_reg.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_v2k_reg.v.log
-cd asicworld code_verilog_tutorial_counter.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_counter.v.log
-cd asicworld code_verilog_tutorial_flip_flop.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_flip_flop.v.log
-cd asicworld code_hdl_models_decoder_2to4_gates.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_decoder_2to4_gates.v.log
-cd asicworld code_hdl_models_parity_using_bitwise.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_parity_using_bitwise.v.log
-cd asicworld code_hdl_models_gray_counter.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_gray_counter.v.log
-cd asicworld code_verilog_tutorial_which_clock.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_which_clock.v.log
-cd asicworld code_verilog_tutorial_explicit.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_explicit.v.log
-cd asicworld code_hdl_models_dff_sync_reset.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_dff_sync_reset.v.log
-cd asicworld code_verilog_tutorial_first_counter.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_first_counter.v.log
-cd asicworld code_hdl_models_lfsr.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_lfsr.v.log
-cd asicworld code_verilog_tutorial_first_counter_tb.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_first_counter_tb.v.log
-cd asicworld code_hdl_models_tff_async_reset.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_tff_async_reset.v.log
-cd asicworld code_hdl_models_d_latch_gates.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_d_latch_gates.v.log
-cd asicworld code_hdl_models_lfsr_updown.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_lfsr_updown.v.log
-cd asicworld code_hdl_models_tff_sync_reset.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_tff_sync_reset.v.log
-cd asicworld code_tidbits_fsm_using_always.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_tidbits_fsm_using_always.v.log
-cd asicworld code_hdl_models_cam.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_cam.v.log
-cd asicworld code_hdl_models_decoder_using_case.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_decoder_using_case.v.log
-cd asicworld code_tidbits_reg_combo_example.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_tidbits_reg_combo_example.v.log
-cd asicworld code_hdl_models_uart.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_uart.v.log
-cd asicworld code_verilog_tutorial_fsm_full_tb.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_fsm_full_tb.v.log
-cd asicworld code_verilog_tutorial_escape_id.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_escape_id.v.log
-cd asicworld code_verilog_tutorial_n_out_primitive.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_n_out_primitive.v.log
-cd asicworld code_verilog_tutorial_d_ff.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_d_ff.v.log
-cd asicworld code_hdl_models_up_down_counter.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_up_down_counter.v.log
-cd asicworld code_tidbits_reg_seq_example.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_tidbits_reg_seq_example.v.log
-cd asicworld code_verilog_tutorial_decoder.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_decoder.v.log
-cd asicworld code_hdl_models_pri_encoder_using_assign.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_pri_encoder_using_assign.v.log
-cd asicworld code_hdl_models_mux_using_if.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_mux_using_if.v.log
-cd asicworld code_tidbits_nonblocking.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_tidbits_nonblocking.v.log
-cd asicworld code_verilog_tutorial_tri_buf.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_tri_buf.v.log
-cd asicworld code_hdl_models_one_hot_cnt.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_one_hot_cnt.v.log
-cd asicworld code_hdl_models_encoder_using_case.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_encoder_using_case.v.log
-cd asicworld code_hdl_models_half_adder_gates.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_half_adder_gates.v.log
-cd asicworld code_verilog_tutorial_always_example.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_always_example.v.log
-cd asicworld code_hdl_models_full_adder_gates.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_full_adder_gates.v.log
-cd asicworld code_hdl_models_decoder_using_assign.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_decoder_using_assign.v.log
-cd asicworld code_verilog_tutorial_comment.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_comment.v.log
-cd asicworld code_hdl_models_arbiter.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_arbiter.v.log
-cd asicworld code_verilog_tutorial_multiply.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_multiply.v.log
-cd asicworld code_verilog_tutorial_mux_21.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_mux_21.v.log
-cd asicworld code_verilog_tutorial_bus_con.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_bus_con.v.log
-cd asicworld code_verilog_tutorial_counter_tb.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_counter_tb.v.log
-cd asicworld code_specman_switch_fabric.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_specman_switch_fabric.v.log
-cd asicworld code_tidbits_asyn_reset.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_tidbits_asyn_reset.v.log
-cd asicworld code_verilog_tutorial_simple_function.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_simple_function.v.log
-cd asicworld code_verilog_tutorial_good_code.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_good_code.v.log
-cd asicworld code_hdl_models_clk_div_45.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_clk_div_45.v.log
-cd asicworld code_tidbits_fsm_using_function.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_tidbits_fsm_using_function.v.log
-cd asicworld code_verilog_tutorial_fsm_full.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_fsm_full.v.log
-cd asicworld code_hdl_models_serial_crc.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_serial_crc.v.log
-cd asicworld code_hdl_models_up_counter_load.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_up_counter_load.v.log
-cd asicworld code_verilog_tutorial_simple_if.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_simple_if.v.log
-cd asicworld code_hdl_models_d_ff_gates.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_d_ff_gates.v.log
-cd asicworld code_hdl_models_mux_using_case.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_mux_using_case.v.log
-cd asicworld code_verilog_tutorial_parity.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_parity.v.log
-cd asicworld code_hdl_models_mux_2to1_gates.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_mux_2to1_gates.v.log
-cd asicworld code_hdl_models_parity_using_assign.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_parity_using_assign.v.log
-cd asicworld code_hdl_models_parity_using_function.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_parity_using_function.v.log
-cd asicworld code_tidbits_wire_example.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_tidbits_wire_example.v.log
-cd asicworld code_hdl_models_clk_div.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_clk_div.v.log
-cd asicworld code_verilog_tutorial_addbit.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_addbit.v.log
-cd asicworld code_hdl_models_GrayCounter.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_GrayCounter.v.log
-cd asicworld code_hdl_models_rom_using_case.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_rom_using_case.v.log
-cd asicworld code_verilog_tutorial_task_global.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_task_global.v.log
-cd asicworld code_tidbits_fsm_using_single_always.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_tidbits_fsm_using_single_always.v.log
-cd asicworld code_hdl_models_up_counter.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_up_counter.v.log
-cd asicworld code_verilog_tutorial_parallel_if.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_parallel_if.v.log
-cd asicworld code_hdl_models_parallel_crc.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_parallel_crc.v.log
-cd asicworld code_hdl_models_encoder_4to2_gates.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_encoder_4to2_gates.v.log
-cd asicworld code_hdl_models_arbiter_tb.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_arbiter_tb.v.log
-cd asicworld code_hdl_models_full_subtracter_gates.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_full_subtracter_gates.v.log
-cd asicworld code_verilog_tutorial_if_else.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_verilog_tutorial_if_else.v.log
-cd asicworld code_hdl_models_encoder_using_if.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l code_hdl_models_encoder_using_if.v.log
-cd proc bug_1268.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l bug_1268.v.log
-cd opt opt_share_extend.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_share_extend.v.log
-cd opt opt_share_cat_multiuser.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_share_cat_multiuser.v.log
-cd opt opt_expr_cmp.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_expr_cmp.v.log
-cd opt opt_share_large_pmux_part.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_share_large_pmux_part.v.log
-cd opt opt_share_add_sub.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_share_add_sub.v.log
-cd opt opt_share_diff_port_widths.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_share_diff_port_widths.v.log
-cd opt opt_share_cat.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_share_cat.v.log
-cd opt opt_share_large_pmux_cat_multipart.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_share_large_pmux_cat_multipart.v.log
-cd opt opt_share_large_pmux_multipart.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_share_large_pmux_multipart.v.log
-cd opt opt_lut.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_lut.v.log
-cd opt opt_share_mux_tree.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_share_mux_tree.v.log
-cd opt opt_rmdff.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_rmdff.v.log
-cd opt opt_rmdff_sat.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_rmdff_sat.v.log
-cd opt opt_share_large_pmux_cat.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l opt_share_large_pmux_cat.v.log
-cd liberty small.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l small.v.log
-cd hana test_parser.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_parser.v.log
-cd hana test_simulation_seq.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_seq.v.log
-cd hana test_simulation_sop.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_sop.v.log
-cd hana test_simulation_always.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_always.v.log
-cd hana test_parse2synthtrans.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_parse2synthtrans.v.log
-cd hana test_simulation_shifter.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_shifter.v.log
-cd hana test_simulation_nand.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_nand.v.log
-cd hana test_simulation_or.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_or.v.log
-cd hana hana_vlib.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l hana_vlib.v.log
-cd hana test_simulation_nor.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_nor.v.log
-cd hana test_simulation_inc.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_inc.v.log
-cd hana test_simulation_and.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_and.v.log
-cd hana test_simulation_xor.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_xor.v.log
-cd hana test_intermout.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_intermout.v.log
-cd hana test_simulation_buffer.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_buffer.v.log
-cd hana test_simulation_techmap_tech.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_techmap_tech.v.log
-cd hana test_simulation_vlib.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_vlib.v.log
-cd hana test_simulation_mux.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_mux.v.log
-cd hana test_simulation_xnor.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_xnor.v.log
-cd hana test_simulation_techmap.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_techmap.v.log
-cd hana test_simulation_decoder.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l test_simulation_decoder.v.log
-cd errors syntax_err11.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err11.v.log
-cd errors syntax_err07.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err07.v.log
-cd errors syntax_err13.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err13.v.log
-cd errors syntax_err02.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err02.v.log
-cd errors syntax_err10.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err10.v.log
-cd errors syntax_err05.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err05.v.log
-cd errors syntax_err06.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err06.v.log
-cd errors syntax_err01.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err01.v.log
-cd errors syntax_err09.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err09.v.log
-cd errors syntax_err08.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err08.v.log
-cd errors syntax_err04.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err04.v.log
-cd errors syntax_err12.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err12.v.log
-cd errors syntax_err03.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l syntax_err03.v.log
-cd svinterfaces svinterface1_ref.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l svinterface1_ref.v.log
-cd svinterfaces svinterface_at_top_ref.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l svinterface_at_top_ref.v.log
-cd svinterfaces svinterface_at_top_tb.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l svinterface_at_top_tb.v.log
-cd svinterfaces svinterface1_tb.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l svinterface1_tb.v.log
-cd svinterfaces svinterface_at_top_tb_wrapper.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l svinterface_at_top_tb_wrapper.v.log
-cd svinterfaces svinterface_at_top_wrapper.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l svinterface_at_top_wrapper.v.log
-cd various attrib05_port_conn.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l attrib05_port_conn.v.log
-cd various shregmap.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l shregmap.v.log
-cd various async.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l async.v.log
-cd various abc9.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l abc9.v.log
-cd various muxpack.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l muxpack.v.log
-cd various pmux2shiftx.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l pmux2shiftx.v.log
-cd various specify.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l specify.v.log
-cd various constmsk_test.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l constmsk_test.v.log
-cd various attrib07_func_call.v -elabuhdm -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l attrib07_func_call.v.log
-cd various constmsk_testmap.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l constmsk_testmap.v.log
-cd arch/common counter.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l counter.v.log
-cd arch/common adffs.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l adffs.v.log
-cd arch/common memory.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l memory.v.log
-cd arch/common add_sub.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l add_sub.v.log
-cd arch/common mul.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l mul.v.log
-cd arch/common fsm.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l fsm.v.log
-cd arch/common logic.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l logic.v.log
-cd arch/common shifter.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l shifter.v.log
-cd arch/common latches.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l latches.v.log
-cd arch/common mux.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l mux.v.log
-cd arch/common tribuf.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l tribuf.v.log
-cd arch/common dffs.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l dffs.v.log
-cd arch/ice40 rom.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l rom.v.log
-cd arch/ice40 dpram.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l dpram.v.log
-cd arch/ice40 macc.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l macc.v.log
-cd arch/xilinx macc.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l macc.v.log
-cd arch/xilinx macc_tb.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l macc_tb.v.log
-cd arch/xilinx xilinx_srl.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l xilinx_srl.v.log
-cd arch/xilinx mul_unsigned.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l mul_unsigned.v.log
-cd arch/ecp5 rom.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l rom.v.log
-cd arch/ecp5 dpram.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l dpram.v.log
-cd arch/ecp5 macc.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l macc.v.log
-cd techmap recursive_map.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l recursive_map.v.log
-cd techmap recursive.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l recursive.v.log
-cd techmap mem_simple_4x1_cells.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l mem_simple_4x1_cells.v.log
-cd techmap mem_simple_4x1_tb.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l mem_simple_4x1_tb.v.log
-cd techmap mem_simple_4x1_map.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l mem_simple_4x1_map.v.log
-cd techmap mem_simple_4x1_uut.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l mem_simple_4x1_uut.v.log
-cd rpc design.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l design.v.log
-cd lut map_not.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l map_not.v.log
-cd lut map_xor.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l map_xor.v.log
-cd lut map_cmp.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l map_cmp.v.log
-cd lut map_mux.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l map_mux.v.log
-cd lut map_and.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l map_and.v.log
-cd lut map_or.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l map_or.v.log
-cd sat expose_dff.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l expose_dff.v.log
-cd sat share.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l share.v.log
-cd sat initval.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l initval.v.log
-cd sat counters.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l counters.v.log
-cd sat counters-repeat.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l counters-repeat.v.log
-cd sat splice.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l splice.v.log
-cd sat asserts.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l asserts.v.log
-cd sat asserts_seq.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l asserts_seq.v.log
-cd simple forgen02.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l forgen02.v.log
-cd simple param_attr.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l param_attr.v.log
-cd simple operators.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l operators.v.log
-cd simple multiplier.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l multiplier.v.log
-cd simple muxtree.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l muxtree.v.log
-cd simple attrib08_mod_inst.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l attrib08_mod_inst.v.log
-cd simple hierdefparam.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l hierdefparam.v.log
-cd simple forgen01.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l forgen01.v.log
-cd simple mem_arst.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l mem_arst.v.log
-cd simple loops.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l loops.v.log
-cd simple attrib06_operator_suffix.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l attrib06_operator_suffix.v.log
-cd simple realexpr.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l realexpr.v.log
-cd simple sincos.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l sincos.v.log
-cd simple attrib03_parameter.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l attrib03_parameter.v.log
-cd simple vloghammer.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l vloghammer.v.log
-cd simple omsp_dbg_uart.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l omsp_dbg_uart.v.log
-cd simple forloops.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l forloops.v.log
-cd simple signedexpr.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l signedexpr.v.log
-cd simple process.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l process.v.log
-cd simple generate.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l generate.v.log
-cd simple constpower.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l constpower.v.log
-cd simple dff_different_styles.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l dff_different_styles.v.log
-cd simple values.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l values.v.log
-cd simple attrib04_net_var.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l attrib04_net_var.v.log
-cd simple dff_init.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l dff_init.v.log
-cd simple i2c_master_tests.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l i2c_master_tests.v.log
-cd simple macros.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l macros.v.log
-cd simple specify.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l specify.v.log
-cd simple always03.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l always03.v.log
-cd simple memory.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l memory.v.log
-cd simple retime.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l retime.v.log
-cd simple usb_phy_tests.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l usb_phy_tests.v.log
-cd simple task_func.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l task_func.v.log
-cd simple arraycells.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l arraycells.v.log
-cd simple carryadd.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l carryadd.v.log
-cd simple always01.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l always01.v.log
-cd simple attrib09_case.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l attrib09_case.v.log
-cd simple graphtest.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l graphtest.v.log
-cd simple repwhile.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l repwhile.v.log
-cd simple fsm.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l fsm.v.log
-cd simple attrib01_module.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l attrib01_module.v.log
-cd simple implicit_ports.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l implicit_ports.v.log
-cd simple arrays01.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l arrays01.v.log
-cd simple constmuldivmod.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l constmuldivmod.v.log
-cd simple scopes.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l scopes.v.log
-cd simple aes_kexp128.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l aes_kexp128.v.log
-cd simple partsel.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l partsel.v.log
-cd simple hierarchy.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l hierarchy.v.log
-cd simple always02.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l always02.v.log
-cd simple wandwor.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l wandwor.v.log
-cd simple fiedler-cooley.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l fiedler-cooley.v.log
-cd simple undef_eqx_nex.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l undef_eqx_nex.v.log
-cd simple paramods.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l paramods.v.log
-cd simple mem2reg.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l mem2reg.v.log
-cd simple rotate.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l rotate.v.log
-cd simple localparam_attr.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l localparam_attr.v.log
-cd simple wreduce.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l wreduce.v.log
-cd simple subbytes.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l subbytes.v.log
-cd simple attrib02_port_decl.v -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l attrib02_port_decl.v.log
-cd sva basic00.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l basic00.sv.log
-cd sva basic04.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l basic04.sv.log
-cd sva basic01.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l basic01.sv.log
-cd sva extnets.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l extnets.sv.log
-cd sva sva_not.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l sva_not.sv.log
-cd sva counter.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l counter.sv.log
-cd sva basic05.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l basic05.sv.log
-cd sva sva_throughout.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l sva_throughout.sv.log
-cd sva basic02.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l basic02.sv.log
-cd sva sva_range.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l sva_range.sv.log
-cd sva basic03.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l basic03.sv.log
-cd svtypes typedef_memory_2.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l typedef_memory_2.sv.log
-cd svtypes typedef_param.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l typedef_param.sv.log
-cd svtypes typedef_scopes.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l typedef_scopes.sv.log
-cd svtypes typedef_simple.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l typedef_simple.sv.log
-cd svtypes typedef_memory.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l typedef_memory.sv.log
-cd svtypes typedef_package.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l typedef_package.sv.log
-cd svinterfaces svinterface1.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l svinterface1.sv.log
-cd svinterfaces svinterface_at_top.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l svinterface_at_top.sv.log
-cd various reg_wire_error.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l reg_wire_error.sv.log
-cd various elab_sys_tasks.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l elab_sys_tasks.sv.log
-cd sat sizebits.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l sizebits.sv.log
-cd simple arrays02.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l arrays02.sv.log
-cd simple defvalue.sv -writepp -parse -nocache -nobuiltin -nonote -noinfo -timescale=1ns/1ns -l defvalue.sv.log